UMK107F103ZZ-T [TAIYO YUDEN]
CAPACITOR, CERAMIC, MULTILAYER, 50V, Y5V, 0.01uF, SURFACE MOUNT, 0603, CHIP;
| 型号： | UMK107F103ZZ-T |
| 厂家： | 
TAIYO YUDEN (U.S.A.), INC |
| 描述： | CAPACITOR, CERAMIC, MULTILAYER, 50V, Y5V, 0.01uF, SURFACE MOUNT, 0603, CHIP 电容器 |
| 文件： | 总16页 (文件大小：2052K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
一般積層セラミックコンデンサ
（高誘電率系・Class 2）
STANDARD MULTILAYER CERAMIC CAPACITORS
(CLASS2 :HIGH DIELECTRIC CONSTANT TYPE)
code Temp.characteristics operating Temp. range
B
－25～＋85℃
－55～＋125℃
－55～＋85℃
－25～＋85℃
－30～＋85℃
B/BJ
X7R
X5R
F
ꢀ
OPERATING TEMP.
F
Y5V
＊042TYPE, 063TYPE, 105TYPEは除く
＊Except for 042TYPE, 063TYPE, 105TYPE
特長ꢀFEATURES
・実装密度の向上が図れます
・Improve Higher Mounting Densities.
・Multilayer block structure provides higher reliability
・A wide range of capacitance values available in standard case sizes.
・モノリシックの構造のため、信
頼性が高い
・同
一形状、静電容量範囲が広い
用途ꢀAPPLICATIONS
・一般電子機器用
・General electronic equipment
・通信
・Communication equipment (cellular phone, PHS, other wireless applica-
tions, etc.)
ꢀ
機器用（携帯電話、PHS、コードレス電話 etc.）
形名表記法ꢀORDERING CODE
1
4
6
7
9
容量許容差〔％〕
個別仕様
定格電圧〔VDC〕
形状寸法（EIA）L×W〔mm〕
公称静電容量〔pF〕
A
J
4
例
K
M
Z
±10
±20
－
標準
042(01005)
063(0201)
105(0402)
107(0603)
0.4×0.2
0.6×0.3
1.0×0.5
1.6×0.8
6.3
102
1000
＋80
－20
L
10
223
22000
E
T
G
U
16
25
35
50
10
8
包装
F
5
テーピング（2mmピッチ・178φ）
製品
厚 み〔mm〕
テーピング（4mmピッチ・178φ）
温度特性
△B,BJ
△F
T
C
P
V
Z
0.2
0.3
0.5
0.8
±10％
ꢀꢀ％
－80
2
＋30
シリーズ名
△＝スペース
M
積層コンデンサ
11
当社管理記号
△
△＝スペース
3
標準
端子電極
K
メッキ品
_
L M K 1 0 5 B J 1 0 4 K V
F ○
1
2
3
4
5
6
7
8
9
10
11
1
4
6
7
9
Capacitance Tolerance〔％〕
Sꢀpecial code
Rated voltage〔VDC〕
Dimensions (case size)（L×W）〔mm
〕
Nominal Capacitance〔pF〕
A
J
4
042(01005)
063(0201)
105(0402)
107(0603)
0.4×0.2
0.6×0.3
1.0×0.5
1.6×0.8
example
K
M
Z
±10
－
Standard products
6.3
102
223
1000
22000
±20
＋80
L
10
ꢀ
－20
E
T
G
U
16
25
35
50
10
8
Packagingꢀ
5
F
T
Tape&Ree（l 2mm pitch・178φ）
Tape&Ree（l 4mm pitch・178φ）
Thickness〔mm〕
Temperature characteristics code
C
P
V
Z
0.2
0.3
0.5
0.8
－55～＋125℃
±15％
2
X7R
△B
ꢀ
Series name
BJ
－55～＋85℃
±15％
X5R
Y5V
11
Multilayer ceramic capacitors
M
－30～＋85℃
Internal code
△F
＋22
％
－82
△
Standard Products
3
△＝Blank space
△＝Blank space
End terminationꢀ
K
Plated
54
外形寸法ꢀEXTERNAL DIMENSIONS
Type（EIA）
□MK042
（01005）
□MK063
（0201）
□MK105
（0402）
□MK107
（0603）
L
W
T
e
0.4±0.02
0.2±0.02
0.2±0.02
0.1±0.03
（0.004±0.001）
0.15±0.05
（0.006±0.002）
0.25±0.10
（0.010±0.002）
0.35±0.25
C
P
V
Z
（0.016±0.001）（0.008±0.001） （0.008±0.001）
0.6±0.03
（0.024±0.001）（0.012±0.001） （0.012±0.001）
1.0±0.05 0.5±0.05 0.5±0.05
（0.039±0.002）（0.020±0.002） （0.020±0.002）
1.6±0.10 ꢀ0.8±0.10 50.8±0.10
（0.063±0.004）（0.031±0.004） （0.031±0.004）
0.3±0.03
0.3±0.03
（0.014±0.010）
Unit：mm（inch）
4
概略バリエーションꢀAVAILABLE CAPACITANCE RANGE
■汎用積層セラミックコンデンサ（General Multilayer Ceramic capacitors）
Type
Temp.char.
WV
042
063
105
107
B/X5R
B/X5R
X5R
F/Y5V
B/X7R
B/X5R
X5R
F/Y5V
B/X7R
F/Y5V
Cap
10V 6.3V 25V 16V 10V 6.3V 6.3V 4V 6.3V 4V 50V 25V 16V 35V 25V 16V 10V 6.3V 6.3V 4V 50V 25V 16V 10V 6.3V 50V 25V 50V 25V
[ pF 3digits ]
[ pF ]
101
151
221
331
471
681
102
152
222
332
472
682
103
153
223
333
473
683
104
224
334
474
105
225
335
475
100
150
220
330
470
680
1000
1500
2200
3300
C
P
V
P
Z
C
4700
6800
P
P
V
10000
15000
22000
33000
47000
68000
100000
220000
330000
470000
1000000
2200000
3300000
4700000
V
Z
Z
Z
V
P
P
V
V
P
V
V
Z
Z
V
V
P
V
V
P
V
V
V
V
P
V
V
V
注:グラフの記号は製品厚 み記号です。Note : Letter codes in shaded areas are thickness codes.
温度特性
温度特性コード
Temperature characteristics
静電容量許容差〔％〕
tanδ〔％〕
Temp. char.Code
準拠規格
温度範囲〔℃〕
基
準温度〔℃〕
Capacitance tolerance
Dissipation factor
容量変化率〔％〕
Applicable standard
Temperature range
Ref. Temp.
Capacitance change
20
25
20
25
±20（M）
±10（K）
＋80
±10
±15
＋30／－80
＋22／－82
－25～85
－55～125
－25～85
－30～85
B
X7R*
F
JIS
EIA
JIS
EIA
BJ
F
2.5%max.**
7.0%max.**
（Z）
ー20ꢀꢀ
Y5V
*：X5Rのみ対応するアイテムがあります。詳細はアイテム一覧を参照ください。
：
** 代表定期な値 を記載しています。詳細はアイテム一覧を参照ください。
*：Some of parts are only applicable to X5R. Please refer to PART NUMBERS table.
：
** The figure indicate typical value. Please refer to PART NUMBERS table.
セレクションガイド
アイテム一覧
特性図
梱包
信
頼性
使用上の注意
Selection Guide
Part Numbers
Electrical Characteristics
Packaging
Reliability Data
Precautions
̶̶̶̶̶̶
P.10
P.56
P.84
P.88
P.94
etc
55
アイテム一覧ꢀPART NUMBERS
042TYPE（01005 case size）
定ꢀ格
EHS
公ꢀꢀ称
静電容量
tanδ
Dissipation Soldering method
factor R:リフロー Reflow soldering Capacitance Thickness
実装条件
静電容量
許 容 差
形ꢀꢀ名
電ꢀ圧
温度特性
厚 ꢀみ
(Environmental
Rated Voltage
Ordering code
（DC）
Hazardous Capacitance
Temp.Char
Substances)
〔pF〕
〔%〕Max. W:フロー Wave soldering
tolerance
hmm（i inch）
LMK042 BJ101□C
LMK042 BJ151□C
LMK042 BJ221□C
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
100
150
220
330
470
10V
LMK042 BJ331□C
LMK042 BJ471□C
LMK042 BJ681□C
LMK042 BJ102□C
JMK042 BJ152□C*
JMK042 BJ222□C*
JMK042 BJ332□C*
JMK042 BJ472□C*
JMK042 BJ682□C*
JMK042 BJ103□C*
5
680
±10％
0.2±0.02
1000
1500
2200
3300
4700
6800
10000
B/X5R
R
±20％ （0.008±0.001）
6.3V
10
形名の□には静電容量許容差記号が入ります。
□Please specify the capacitance tolerance code.
* Test voltage of Loading at high temperature test is 1.5 time of the rated voltage.
*
高温負荷試験の試験電圧は定格電圧の1.5倍
063TYPE（0201 case size）
定ꢀ格
EHS
公ꢀꢀ称
静電容量
tanδ
Dissipation Soldering method
factor R:リフロー Reflow soldering Capacitance Thickness
実装条件
静電容量
許 容 差
形ꢀꢀ名
電ꢀ圧
温度特性
厚 ꢀみ
(Environmental
Rated Voltage
Ordering code
（DC）
Hazardous Capacitance
Temp.Char
Substances)
〔pF〕
〔%〕Max. W:フロー Wave soldering
tolerance
hmm（i inch）
TMK063 BJ101□P
TMK063 BJ151□P
TMK063 BJ221□P
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
100
150
220
330
470
680
1000
1500
2200
25V
TMK063 BJ331□P
TMK063 BJ471□P
TMK063 BJ681□P
TMK063 BJ102□P
EMK063 BJ152□P
EMK063 BJ222□P
EMK063 BJ332□P
LMK063 BJ472□P
LMK063 BJ682□P
LMK063 BJ103□P
LMK063 BJ223□P*
JMK063 BJ473□P*
JMK063 BJ104□P*
JMK063 BJ224MP*
AMK063 BJ224MP*
AMK063 BJ334MP*
AMK063 BJ474MP*
JMK063 F223ZP
JMK063 F473ZP
AMK063 F104ZP
3.5
±10％
±20％
B/X5R
16V
10V
3300
4700
6800
0.3±0.03
（0.012±0.001）
5
R
10000
22000
47000
100000
220000
220000
330000
470000
22000
47000
100000
7.5
10
6.3V
4V
X5R
±20％
6.3V
4V
＋80％
－20％
F/Y5V
12.5
形名の□には静電容量許容差記号が入ります。
□Please specify the capacitance tolerance code.
* Test voltage of Loading at high temperature test is 1.5 time of the rated voltage.
*
高温負荷試験の試験電圧は定格電圧の1.5倍
56
アイテム一覧ꢀPART NUMBERS
105TYPE（0402 case size）
定ꢀ格
電ꢀ圧
EHS
公ꢀꢀ称
静電容量
tanδ
Dissipation Soldering method
factor R:リフロー Reflow soldering Capacitance Thickness
実装条件
静電容量
許 容 差
形ꢀꢀ名
温度特性
厚 ꢀみ
(Environmental
Rated Voltage
Ordering code
（DC）
Hazardous Capacitance
Temp.Char
Substances)
〔pF〕
〔%〕Max. W:フロー Wave soldering
tolerance 〔mm（〕inch）
UMK105 BJ221□V
UMK105 BJ331□V
UMK105 BJ471□V
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
220
330
470
680
1000
1500
2200
3300
100000
4700
4
UMK105 BJ681□V
B/X7R
50V
UMK105 BJ102□V
2.5
UMK105 BJ152□V
UMK105 BJ222□V
UMK105 BJ332□V
35V
25V
GMK105 BJ104□V*
TMK105 BJ472□V
TMK105 BJ682□V
TMK105 BJ103□V
TMK105 BJ104□V*
EMK105 BJ153□V
EMK105 BJ223□V
EMK105 BJ333□V
EMK105 BJ473□V
EMK105 BJ104□V*
EMK105 BJ104□V*
EMK105 BJ224□V*
LMK105 BJ104□V
LMK105 BJ224□V*
LMK105 BJ474□V*
LMK105 BJ105□V*
JMK105 BJ224□V*
JMK105 BJ474□V*
JMK105 BJ105□V*
JMK105 BJ225MV*
AMK105 BJ335MV*
AMK105 BJ475MV*
UMK105 F103 Z V
TMK105 F223 Z V
EMK105 F473 Z V
EMK105 F104 Z V
LMK105 F224 Z V
JMK105 F474 Z V
JMK105 F105 Z V*
B/X5R
B/X7R
B/X5R
5
2.5
6800
10000
100000
15000
22000
33000
47000
100000※
100000
220000
100000
220000
470000
1000000
220000
470000
1000000
220000
330000
470000
10000
22000
47000
100000
220000
470000
1000000
3.5
5
±10％
±20％
3.5
B/X7R
16V
10V
R
0.5±0.05
5
10
5
B/X5R
X5R
6.3V
4V
10
±20％
50V
25V
5
7
9
11
16
20
16V
10V
6.3V
＋80％
－20％
F/Y5V
形名の□には静電容量許容差記号が入ります。
高温負荷試験の試験電圧は定格電圧の1.5倍
※品名末尾にRが付きます。
※Internal Code shall be R.
□Please specify the capacitance tolerance code.
*
* Test voltage of Loading at high temperature test is 1.5 time of the rated voltage.
107TYPE（0603 case size）
定ꢀ格
EHS
公ꢀꢀ称
静電容量
tanδ
Dissipation Soldering method
factor R:リフロー Reflow soldering Capacitance Thickness
実装条件
静電容量
許 容 差
形ꢀꢀ名
電ꢀ圧
温度特性
厚 ꢀみ
(Environmental
Rated Voltage
Ordering code
（DC）
Hazardous Capacitance
Temp.Char
Substances)
〔pF〕
〔%〕Max. W:フロー Wave soldering
tolerance 〔mm（〕inch）
UMK107 B102□Z
UMK107 B152□Z
UMK107 B222□Z
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
1000
1500
2200
3300
4700
50V
UMK107 B332□Z
UMK107 B472□Z
UMK107 B682□Z
UMK107 B103□Z
TMK107 B153□Z
TMK107 B223□Z
UMK107 F103 Z Z
UMK107 F223 Z Z
TMK107 F473 Z Z
TMK107 F104 Z Z
±10％
±20％
B/X7R
2.5
6800
0.8±0.10
（0.031±0.004）
W, R
10000
15000
22000
10000
22000
47000
100000
25V
50V
25V
＋80％
－20％
5
F/Y5V
形名の□には静電容量許容差記号が入ります。
□Please specify the capacitance tolerance code.
57
梱包ꢀPACKAGING
①最小受注単位数 Minimum Quantity
■テーピング梱包ꢀ Taped packagingꢀ
標準数量
製品
厚 み
Standard quantity
[ pcs ]
形式（EIA）
Thickness
Type
紙テープ エンボステープ
code
mm（inch）
paper
Embossed tape
□MK04（2 01005
）
0.2（0.008）
0.3（0.012）
0.3（0.012）
0.45（0.018）
C
P
15000
̶
̶
□MK063（0201）
15000
P
□2K09（6 0302）
10000
̶
K
□MK105（0402）
□VK105（0402）
V, W
W
K
0.5（0.020）
10000
̶
0.45（0.018）
0.5（0.020）
4000
̶
4000
V
̶
□MK107（0603）
□WK10（7 0306）
A
0.8（0.031）
4000
̶
Z
0.8（0.031）
0.6（0.024）
0.45（0.018）
0.85（0.033）
1.25（0.049）
0.85（0.033）
0.85（0.033）
0.85（0.033）
1.15（0.045）
1.25（0.049）
1.6（0.063）
0.85（0.033）
1.15（0.045）
1.5（0.059）
1.9（0.075）
2.0ma（x 0.079）
2.5（0.098）
1.9（0.075）
2.5（0.098）
3.2（0.125）
A
4000
4000
4000
4000
̶
4000
4000
4000
̶
̶
̶
̶
3000
̶
□2K11（0 0504）
B
K
□MK212（0805）
□WK21（2 0508）
D
G
D
D
D
F
□4K21（2 0805）
□2K21（2 0805）
③バルクカセットꢀBulk Cassette
̶
̶
□MK316（1206）
□WK31（6 0612）
̶
̶
3000
2000
G
L
D
F
̶
2000
H
N
Y
□MK325（1210）
□MK432（1812）
̶
̶
̶
2000
500,1000
1000
M
Y
M
U
̶
500
※プレスポケットタイプは、
ꢀボトムテープ無し。
②テーピング材質ꢀTaping material
Unit：mm（inch）
105, 107, 212形状で個
別対応致しますのでお問い合せ下さい。
Please contact any of our offices for accepting your requirement accord-
ing to dimensions 0402, 0603, 0805.(inch)
84
梱包ꢀPACKAGING
③テーピング寸法ꢀTaping dimensionsꢀ
ꢀ紙テープꢀPaper Tape（8mm幅（）0.315inches wide）
エンボステープꢀEmbossed tape（8mm幅（）0.315inches wide）
部品
挿入角穴
4
T1
2.0±0.05 2.0±0.05
チップ挿入部
Chip Cavity
B
挿入ピッチ テープ厚 み
Type
Insertion Pitch Tape Thickness
（EIA）
1
A
F
T
T
チップ挿入部
Chip cavity
挿入ピッチ テープ厚 み
Type
0.25
0.45
2.0±0.05
0.36max 0.27max.
Insertion Pitch Tape Thickness
□MK042（01005）
（EIA）
（0.010）
0.37
（0.018） （0.079±0.002）（0.014）（0.011）
52.0±0.05 0.45max 0.42max.
A
B
F
K
T
0.67
1.0
1.8
1.3max. 0.25±0.1
□MK063（0201）
□WK107（0306）
□MK212（0805）
（0.016）
（0.027） （0.079±0.002）（0.018）（0.017）
（0.039） （0.071）
1.655 2.4
（0.051max.）（0.01±0.004）
Unit：mm（inch）
部品
挿入角穴
（0.065） （0.094）
2.0 3.6
（0.079） （0.142）
2.8 3.6
（0.110） （0.142）
4.0±0.1
（0.157±0.004）2.5max. 0.6max
（0.098max.）（0.024max.）
3.4max.
□MK316（1206）
□MK325（1210）
（0.134max.）
Unit：mm（inch）
2.0±0.05 2.0±0.05
エンボステープꢀEmbossed tape（12mm幅（）0.472inches wide）
チップ挿入部
Chip Cavity
挿入ピッチ テープ厚 み
Type
Insertion Pitch Tape Thickness
（EIA）
A
B
F
T
0.72
（0.028）
0.655
1.02
52.0±0.05 0.45max.(0.018max)
□2K096（0302）
□MK105（0402）
（0.040） （0.079±0.002）0.6max.(0.024max)
1.155
52.0±0.05
0.8max.
□VK105（0402） （0.026）
（0.045） （0.079±0.002）（0.031max.）
Unit：mm（inch）
チップ挿入部
Chip cavity
挿入ピッチ テープ厚 み
Type
Insertion Pitch Tape Thickness
（EIA）
A
B
F
K
T
3.7
4.9
8.0±0.1
4.0max. 0.6max.
□MK432（1812）
（0.146）
（0.193） （0.315±0.004） （0.157max.）（0.024max.）
Unit：mm（inch）
チップ挿入部
Chip Cavity
挿入ピッチ テープ厚 み
Type
Insertion Pitch Tape Thickness
（EIA）
A
B
F
T
□MK10（7 0603）
□WK10（7 0306）
1.0
1.8
4.0±0.1
1.1max.
（0.039）
1.15
（0.071） （0.157±0.004） （0.043max.）
1.55
4.0±0.1
1.0max.
□2K110（0504）
（0.045）
（0.061） （0.157±0.004） （0.039max.）
□MK212（0805）
□WK212（0508）
1.655
2.4
□4K212（0805） （0.065）
□2K212（0805）
（0.094）
4.0±0.1
1.1max.
（0.157±0.004） （0.043max.）
□MK316（1206）
□WK316（0612）
2.0
3.6
（0.079）
（0.142）
Unit：mm（inch）
85
④リーダー部／空部ꢀLeader and Blank portionꢀ
160mm以上
（6.3inches or more
100mm以上
）
（3.94inches or more）
引き出し方向
Direction of tape feed
400mm以上
（15.7inches or more）
⑤リール寸法ꢀReel sizeꢀ
⑥トップテープ強度ꢀTop Tape Strengthꢀ
トップテープのはがし力は下図矢印方向にて0.1～0.7Nとなります。
The top tape requires a peel-off force of 0.1～0.7N in the direction of the
arrow as illustrated below.
86
RELIABILITY DATA
1/3
Multilayer Ceramic Capacitor Chips
Specified Value
Temperature Compensating（Class 1）
Item
High Permitivity（Class 2）
Test Methods and Remarks
Standard
High Frequency Type
Standard Note1
BJ：－55 to ＋125℃
High Value
1.Operating Temperature
Range
－25 to ＋85℃
－55 to ＋125℃
High Capacitance Type
High Capacitance Type
BJ（X7R）：－55～＋125℃, BJ（X5R）：－55～＋85℃
E（Y5U）：－30～＋85℃, F（Y5V）：－30～＋85℃
BJ（X7R）：－55～＋125℃, BJ（X5R）：－55～＋85℃
E（Y5U）：－30～＋85℃, F（Y5V）：－30～＋85℃
F：－25 to ＋85℃
BJ：－55 to ＋125℃
F：－25 to ＋85℃
50VDC,25VDC
2.Storage Temperature
Range
－25 to ＋85℃
－55 to ＋125℃
4
3.Rated Voltage
16VDC
50VDC
50VDC,35VDC,25VDC
16VDC,10VDC,6.3VDC
4DVC, 2.5VDC
50VDC,25VDC,
16VDC
4.Withstanding Voltage
No abnormality
No breakdown or damage
Applied voltage: Rated voltage×3 （Class 1）
Rated voltage×2.5（Class 2）
N o b re a k d o w n o r
damage
Between terminals
Duration: 1 to 5 sec.
Charge/discharge current: 50mA max.（Class 1,2）
5.Insulation Resistance
500 MΩμF. or 10000 MΩ., whichever is the Applied voltage: Rated voltage
10000 MΩ min.
smaller.
Duration: 60±5 sec.
Note 5
Charge/discharge current: 50mA max.
6.Capacitance（Tolerance）
0.5 to 2 pF : ±0.1 pF
2.2 to 5.1 pF : ±5%
BJ: ±10%, ±20%
＋80
BJ：±10％、±20％
F：－20％／＋80％
0.5 to 5 pF: ±0.25 pF
1 to 10pF: ±0.5 pF
5 to 10 pF: ±1 pF
11 pF or over: ± 5%
±10%
Measuring frequency：
Class1： 1ＭHz±10%（C≦1000pF）
F：
%
－20
1ｋHz±10%（C＞1000pF）
Class2： 1ｋHz±10%（C≦10μF）
120Hz±10Hz（C＞10μF）
Measuring voltage：
Note 4
Class1：0.5～5Vrms（C≦1000pF）
1±0.2Vrms（C＞1000pF）
105TYPER△, S△, T△, U△ only
0.5～2pF: ±0.1pF
Class2： 1±0.2Vrms（C≦10μF）
0.5±0.1Vrms（C＞10μF）
2.2～20pF: ±5%
Bias application: None
7.Q or Tangent of Loss Angle
（tan δ）
R e f e r t o d e t a i l e d BJ: 2.5% max（. 50V, 25V）
Under 30 pF
BJ：2.5％ max.
F：7％ max.
Note 4
Multilayer:
Measuring frequency：
specification
F: 5.0% max.（50V, 25V）
Note 4
: Q≧400 ＋ 20C
Class1： 1ＭHz±10%（C≦1000pF）
30 pF or over : Q≧1000
C= Nominal capacitance
1ｋHz±10%（C＞1000pF）
Class2： 1ｋHz±10%（C≦10μF）
120Hz±10Hz（C＞10μF）
Measuring voltage：
Note 4ꢀꢀꢀꢀ Class1：0.5～5Vrms（C≦1000pF）
1±0.2Vrms（C＞1000pF）
Class2： 1±0.2Vrms（C≦10μF）
0.5±0.1Vrms（C＞10μF）
Bias application: None
HighーFrequencyーMultilayer:
Measuring frequency: 1GHz
Measuring equipment: HP4291A
Measuring jig: HP16192A
8.Temperature
（Without
CH：0±60
BJ：±10％（－25～85℃）
＋30
CK：0±250
According to JIS C 5102 clause 7.12.
Temperature compensating:
BJ：±10％
Characteristic
voltage ap-
RH：－220±60
（ppm/℃）
F：
％（－25～85℃）
－80
CJ：0±120
ꢀ（－25～＋85℃）
F：＋30％／－80％
ꢀ（－25～＋85℃）
BJ（X7R、X5R）：
ꢀꢀ±15％
of Capacitance
BJ（X7R）：±15％
CH：0±60
Measurement of capacitance at 20℃ and 85℃ shall be
made to calculate temperature characteristic by the fol-
lowing equation.
plication）
＋22
F（Y5V）：ꢀꢀ％
CG：0±30
－82
RH：－220±60
SK：－330±250
SJ：－330±120
SH：－330±60
TK：－470±250
TJ：－470±120
UK：－750±250
UJ：－750±120
SL ： ＋ 350 to ー 1000
（ppm/℃）
（C85ー C20
C20×△T
）
× 106ꢀ（ppm/℃）
F（Y5V）：
High permitivity:
ꢀꢀ＋22％／－82％
Change of maximum capacitance deviation in step 1 to 5
Temperature at step 1: ＋20℃
Temperature at step 2: minimum operating temperature
Temperature at step 3: ＋20℃（Reference temperature）
Temperature at step 4: maximum operating temperature
Temperature at step 5: ＋20℃
Reference temperature for X7R, X5R, Y5U and Y5V shall be ＋25℃
9.Resistance to Flexure of
Appearance:
Appearance:
Appearance:
Warp: 1mm
Testing board: glass epoxyーresin substrate
Thickness: 1.6mm（063 TYPE : 0.8mm）
The measurement shall be made with board in the bent position.
Substrate
No abnormality
No abnormality
No abnormality
Capacitance change: Capacitance change:
Capacitance change:
Within ±5% or ±0.5 pF,
whichever is larger.
Within±0.5 pF
BJ：Within ±12.5%
F：Within ±30%
89
RELIABILITY DATA
2/3
Multilayer Ceramic Capacitor Chips
Specified Value
Temperature Compensating（Class 1）
Standard High Frequency Type
Item
High Permittivity（Class 2）
Standard Note1 High Value
Test Methods and Remarks
10.Body Strength
No mechanical dam-
age.
High Frequency Multilayer:
Applied force: 5N
Duration: 10 sec.
4
11.Adhesion of Electrode
No separation or indication of separation of electrode.
Applied force: 5N
（01005, 0201, 0302 TYPE 2N）
Duration: 30±5 sec.
12.Solderability
At least 95% of terminal electrode is covered by new solder.
Solder temperature: 230±5℃
Duration: 4±1 sec.
13.Resistance to soldering
Appearance: No ab- Appearance: No ab- Appearance: No abnormality
Preconditioning: Thermal treatment（at 150℃ for 1 hr）
（Applicable to Class 2.）
normality
normality
Capacitance change: Within ±7.5%（BJ）
Within ±20%（F）
Capacitance change: Capacitance change:
W i t h i n ± 2.5% o r Within ±2.5%
±0.25pF, whichever is Q: Initial value
Solder temperature: 270±5℃
tan δ: Initial value
Note 4 Duration: 3±0.5 sec.
Insulation resistance: Initial value
Preheating conditions: 80 to 100℃, 2 to 5 min. or 5 to 10 min.
150 to 200℃, 2 to 5 min. or 5 to 10 min.
Recovery: Recovery for the following period under the
standard condition after the test.
larger.
Insulation resistance: Withstanding voltage（between terminals）: No
Initial value abnormality
Q: Initial value
Insulation resistance: Withstanding voltage
Initial value （between terminals）:
6～24 hrs（Class 1）
Withstanding voltage No abnormality
（between terminals）:
24±2 hrs（Class 2）
No abnormality
14.Thermal shock
Appearance: No ab- Appearance: No ab- Appearance: No abnormality
Preconditioning: Thermal treatment（at 150℃ for 1 hr）
（Applicable to Class 2.）
normality
normality
Capacitance change: Within ±7.5%（BJ）
Within ±20%（F）
Capacitance change: Capacitance change:
W i t h i n ± 2.5% o r Within ±0.25pF
±0.25pF, whichever is Q: Initial value
Conditions for 1 cycle:
Note 4 Step 1: Minimum operating temperature ＋－
℃
30±3 min.
2 to 3 min.
30±3 min.
2 to 3 min.
0
tan δ: Initial value
3
Insulation resistance: Initial value
Step 2: Room temperature
Insulation resistance: Withstanding voltage（between terminals）: No Step 3: Maximum operating temperature －＋
℃
0
3
larger.
Q: Initial value
Initial value
abnormality
Step 4: Room temperature
Number of cycles: 5 times
Insulation resistance: Withstanding voltage
Initial value （between terminals）:
Recovery after the test: 6～24 hrs（Class 1）
24±2 hrs（Class 2）
Withstanding voltage No abnormality
（between terminals）:
No abnormality
Appearance: No ab- Appearance: No ab-
15.Damp Heat（steady state） Appearance: No ab- Appearance: No ab-
normality normality
Multilayer：
normality
normality
Preconditioning: Thermal treatment（at 150℃ for 1 hr）
（Applicable to Class 2.）
Capacitance change:
BJ: Within ±12.5%
Capacitance change:
BJ:Within ±12.5%
Note 4
Capacitance change: Capacitance change:
Within ±5% or ±0.5pF, Within ±0.5pF,
Temperature: 40±2℃
whichever is larger.
Q:
Insulation resistance: F: Within ±30%
1000 MΩ min.
Humidity: 90 to 95% RH
＋24
tan δ: BJ: 5.0% max. tan δ:
Duration: 500 － hrs
0
C≧30 pF : Q≧350
10 ≦ C＜ 30 pF: Q≧
275 ＋ 2.5C
F: 7.5% max. BJ: 5.0% max. Note 4. Recovery: Recovery for the following period under the
Note 4
F: 11.0% max.
standard condition after the removal from test chamber.
6～24 hrs（Class 1）
Insulation resistance: Insulation resistance:
50 MΩμF or 1000 MΩ 50 MΩμF or 1000 MΩ
C＜10 pF
＋ 10C
: Q≧200
24±2 hrs（Class 2）
whichever is smaller.
whichever is smaller.
HighーFrequency Multilayer:
Temperature: 60±2℃
Note 5
Note 5
C: Nominal capacitance
Insulation resistance:
1000 MΩ min.
Humidity: 90 to 95% RH
＋24
Duration: 500 － hrs
0
Recovery: Recovery for the following period under the
standard condition after the removal from test chamber.
6～24 hrs（Class 1）
91
RELIABILITY DATA
3/3
Multilayer Ceramic Capacitor Chips
Specified Value
Temperature Compensating（Class 1）
Standard High Frequency Type
16.Loading under Damp Heat Appearance: No ab- Appearance: No ab-
Item
High Permittivity（Class 2）
Test Methods and Remarks
Standard Note1
High Value
According to JIS C 5102 Clause 9. 9.
Multilayer:
Appearance: No ab-
normality
Appearance: No ab-
normality
normality
normality
Capacitance change: Capacitance change:
Within ±7.5% or ± C≦2 pF:Within±0.4 pF
0.75pF, whichever is C＞2 pF: Within ±0.75
Preconditioning: Voltage treatment（Class 2）
Temperature: 40±2℃
Capacitance change:
BJ: Within ±12.5%
F: Within ±30%
Note 4
Capacitance change:
BJ：Within±12.5％
F：Within±30％
Note 4
4
Humidity: 90 to 95% RH
＋24
larger.
pF
Duration: 500 － hrs
0
Q: C≧30 pF: Q≧200
C＜30 pF: Q≧100 ＋ tance
10C/3
C ： Nominal capaci-
Applied voltage: Rated voltage
tan δ: BJ: 5.0% max.
F: 7.5% max.
tanδ：
BJ：5.0％max.
F：11％max.
Charge and discharge current: 50mA max.（Class 1,2）
Recovery: Recovery for the following period under the standard
condition after the removal from test chamber.
6～24 hrs（Class 1）
24±2 hrs（Class 2）
HighーFrequency Multilayer:
Insulation resistance:
Note 4
C ： Nominal capaci- 500 MΩ min.
tance
Insulation resistance:
25 MΩμF or 500 MΩ,
whichever is the smaller.
Note 5
Note 4
Insulation resistance:
25 MΩμF or 500 MΩ,
whichever is the smaller.
Note 5
Insulation resistance:
500 MΩ min.
Temperature: 60±2℃
Humidity: 90 to 95% RH
＋24
Duration: 500
hrs
－
0
Applied voltage: Rated voltage
Charge and discharge current: 50mA max.
Recovery: 6～24 hrs of recovery under the standard
condition after the removal from test chamber.
17.Loading at High Tempera-
Appearance: No ab- Appearance: No ab-
According to JIS C 5102 clause 9.10.
Multilayer:
Appearance: No abnormality
Capacitance change:
BJ：Within±12.5％
Within±20％※※
Within±25％※※
F：Within±30％
Note 4
ture
normality
normality
Appearance: No ab-
normality
Capacitance change:
Within ±3% or
±0.3pF, whichever is
larger.
Capacitance change:
Within ±3% or ±
0.3pF, whichever is
larger.
Preconditioning: Voltage treatment（Class 2）
Temperature:125±3℃（Class 1, Class 2: B, BJ（X7R）
）
Capacitance change:
BJ: Within ±12.5%
F: Within ±30%
Note 4
85±2℃（Class 2: BJ,F）
＋48
Duration: 1000－ hrs
0
Q: C≧30 pF : Q≧350 Insulation resistance:
Applied voltage: Rated voltage×2 Note 6
10≦C＜30 pF: Q≧275
＋ 2.5C
C＜10 pF: Q≧200 ＋
10C
1000 MΩ min.
Recovery: Recovery for the following period under the
standard condition after the removal from test chamber.
As for Ni product, thermal treatment shall be performed
prior to the recovery.
tan δ:
BJ: 4.0% max.
tanδ：
BJ：5.0％max.
F：11％max.ꢀ
Note 4
F: 7.5% max.
Note 4
C：Nominal
capacitance
ꢀꢀꢀ6～24 hrs（Class 1）
ꢀꢀꢀ 24±2 hrs（Class 2）
HighーFrequency Multilayer:
Insulation resistance:
50 MΩμF or 1000 MΩ,
whichever is smaller.
Note 5
Insulation resistance:
50 MΩμF or 1000 MΩ,
whichever is smaller.
Note 5
Insulation resistance:
1000 MΩ min.
Temperature: 125±3℃（Class 1）
＋48
Duration: 1000－ hrs
0
Applied voltage: Rated voltage×2
Recovery: 6～24 hrs of recovery under the standard
condition after the removal from test chamber.
Note 1
Note 2
Note 3
:For 105 type, specified in "High value".
:Thermal treatment（Multilayer）: 1 hr of thermal treatment at 150 ＋0 /－10 ℃ followed by 24±2 hrs of recovery under the standard condition shall be performed before the measurement.
Voltage treatment（Multilayer）: 1 hr of voltage treatment under the specified temperature and voltage for testing followed by 24±2 hrs of recovery under the standard condition shall be performed before the measurement.
:
Note 4, 5 :The figure indicates typical inspection. Please refer to individual specifications.
Note 6 :Some of the parts are applicable in rated voltage×1.5. Please refer to individual specifications.
Note on standard condition: "standard condition" referred to herein is defined as follows: 5 to 35℃ of temperature, 45 to 85% relative humidity, and 86 to 106kPa of air pressure.
When there are questions concerning measurement results: In order to provide correlation data, the test shall be conducted under condition of 20±2℃ of temperature, 60 to 70% relative
humidity, and 86 to 106kPa of air pressure. Unless otherwise specified, all the tests are conducted under the "standard condition."
93
PRECAUTIONS
1/6
Precautions on the use of Multilayer Ceramic Capacitors
Stages
Precautions
Technical considerations
1.Circuit Design
Verification of operating environment, electrical rating and per-
formance
1. A malfunction in medical equipment, spacecraft, nuclear
reactors, etc. may cause serious harm to human life or have
severe social ramifications. As such, any capacitors to be
used in such equipment may require higher safety and/or
reliability considerations and should be clearly differentiated
from components used in general purpose applications.
4
Operating Voltage（Verification of Rated voltage）
1. The operating voltage for capacitors must always be lower
than their rated values.
If an AC voltage is loaded on a DC voltage, the sum of the
two peak voltages should be lower than the rated value of
the capacitor chosen. For a circuit where both an AC and a
pulse voltage may be present, the sum of their peak voltages
should also be lower than the capacitor's rated voltage.
2. Even if the applied voltage is lower than the rated value, the
reliability of capacitors might be reduced if either a high fre-
quency AC voltage or a pulse voltage having rapid rise time
is present in the circuit.
1.The following diagrams and tables show some examples of recommended patterns to
prevent excessive solder amourts.（larger fillets which extend above the component
end terminations）
2.PCB Design
Pattern configurations
（Design of Land-patterns）
1. When capacitors are mounted on a PCB, the amount of
solder used（size of fillet）can directly affect capacitor per-
formance. Therefore, the following items must be carefully
considered in the design of solder land patterns:
（1）The amount of solder applied can affect the ability of
chips to withstand mechanical stresses which may lead
to breaking or cracking. Therefore, when designing
land-patterns it is necessary to consider the appropri-
ate size and configuration of the solder pads which in
turn determines the amount of solder necessary to form
the fillets.
Examples of improper pattern designs are also shown.
（1）Recommended land dimensions for a typical chip capacitor land patterns for PCBs
Recommended land dimensions for wave-soldering（unit: mm）
（2）When more than one part is jointly soldered onto the
same land or pad, the pad must be designed so that each
component's soldering point is separated by solder-resist.
Type
107
1.6
0.8
212
2.0
316
3.2
1.6
325
3.2
2.5
L
Size
W
51.25
A
0.8～1.0 1.0～1.4 1.8～2.5 1.8～2.5
0.5～0.8 0.8～1.5 0.8～1.7 0.8～1.7
0.6～0.8 0.9～1.2 1.2～1.6 1.8～2.5
B
C
Recommended land dimensions for reflow-soldering（unit: mm）
Type
042
0.4
0.2
063
0.6
0.3
105
1.0
0.5
107
1.6
0.8
212
2.0
316
3.2
1.6
325
3.2
2.5
432
4.5
3.2
L
Size
W
51.25
A
0.15～0.25 0.20～0.30 0.45～0.55 0.6～0.8 0.8～1.2 1.8～2.5 1.8～2.5 2.5～3.5
0.10～0.20 0.20～0.30 0.40～0.50 0.6～0.8 0.8～1.2 1.0～1.5 1.0～1.5 1.5～1.8
0.15～0.30 0.25～0.40 0.45～0.55 0.6～0.8 0.9～1.6 1.2～2.0 1.8～3.2 2.3～3.5
B
C
Excess solder can affect the ability of chips to withstand mechanical stresses. There-
fore, please take proper precautions when designing land-patterns.
Type 212（4 circuits）
2.0
L
1.25
W
a
b
c
d
0.5～0.6
0.5～0.6
0.2～0.3
0.5
Type 212（2 circuits） 110（2 circuits）096（2 circuits）
L
2.0
1.37
1.0
0.9
0.6
1.25
W
a
b
c
d
0.5～0.6
0.5～0.6
0.5～0.6
1.0
0.35～0.45 0.25～0.35
0.55～0.65 0.15～0.25
0.3～0.4
0.64
0.15～0.25
0.45
95
PRECAUTIONS
2/6
Precautions on the use of Multilayer Ceramic Capacitors
Stages
Precautions
Technical considerations
LWDC Recommended land dimensions for reflow-soldering
4
105
1.0
107
51.6
0.8
212
2.0
316
3.2
1.6
Type
W
0.52
1.25
L
A
B
C
0.18～0.22 0.25～0.3 0.5～0.7 0.8~1.0
0.2～0.25 0.3～0.4 0.4～0.5 0.4~0.5
0.9～1.1 1.5～1.7 1.9～2.1 3.0～3.4
（unit: mm）
2.PCB Design
（2）Examples of good and bad solder application
Not recommended
Recommended
Items
Mixed mounting
of SMD and
leaded compo-
nents
Component
placement close
to the chassis
Hand-soldering
of leaded
components
near mounted
components
Horizontal
component
placement
Pattern configurations
1-1. The following are examples of good and bad capacitor layout; SMD capacitors should
（Capacitor layout on panelized [breakaway] PC boards）
1. After capacitors have been mounted on the boards, chips
can be subjected to mechanical stresses in subsequent
manufacturing processes（PCB cutting, board inspection,
mounting of additional parts, assembly into the chassis, wave
soldering the reflow soldered boards etc.） For this reason,
planning pattern configurations and the position of SMD ca-
pacitors should be carefully performed to minimize stress.
be located to minimize any possible mechanical stresses from board warp or deflection.
Not recommended
Recommended
Deflection of
the board
1-2. To layout the capacitors for the breakaway PC board, it should be noted that the
amount of mechanical stresses given will vary depending on capacitor layout. The
example below shows recommendations for better design.
1-3. When breaking PC boards along their perforations, the amount of mechanical stress
on the capacitors can vary according to the method used. The following methods
are listed in order from least stressful to most stressful: push-back, slit, V-grooving,
and perforation. Thus, any ideal SMD capacitor layout must also consider the PCB
splitting procedure.
97
PRECAUTIONS
3/6
Precautions on the use of Multilayer Ceramic Capacitors
Stages
Precautions
Technical considerations
3.Considerations for auto-
Adjustment of mounting machine
1. If the lower limit of the pick-up nozzle is low, too much force may be imposed on the
capacitors, causing damage. To avoid this, the following points should be considered
before lowering the pick-up nozzle:
matic placement
1. Excessive impact load should not be imposed on the ca-
pacitors when mounting onto the PC boards.
2. The maintenance and inspection of the mounters should be
conducted periodically.
（1）The lower limit of the pick-up nozzle should be adjusted to the surface level of the
PC board after correcting for deflection of the board.
4
（2）The pick-up pressure should be adjusted between 1 and 3 N static loads.
（3）To reduce the amount of deflection of the board caused by impact of the pick-up
nozzle, supporting pins or back-up pins should be used under the PC board. The fol-
lowing diagrams show some typical examples of good pick-up nozzle placement:
Not recommended
Recommended
Single-sided
mounting
Double-sided
mounting
2. As the alignment pin wears out, adjustment of the nozzle height can cause chipping or
cracking of the capacitors because of mechanical impact on the capacitors. To avoid
this, the monitoring of the width between the alignment pin in the stopped position, and
maintenance, inspection and replacement of the pin should be conducted periodically.
Selection of Adhesives
1. Some adhesives may cause reduced insulation resistance. The difference between
the shrinkage percentage of the adhesive and that of the capacitors may result in
stresses on the capacitors and lead to cracking. Moreover, too little or too much
adhesive applied to the board may adversely affect component placement, so the fol-
lowing precautions should be noted in the application of adhesives.
1. Mounting capacitors with adhesives in preliminary assembly,
before the soldering stage, may lead to degraded capacitor
characteristics unless the following factors are appropriately
checked; the size of land patterns, type of adhesive, amount
applied, hardening temperature and hardening period.
Therefore, it is imperative to consult the manufacturer of the
adhesives on proper usage and amounts of adhesive to use.
（1）Required adhesive characteristics
a. The adhesive should be strong enough to hold parts on the board during the mount-
ing & solder process.
b. The adhesive should have sufficient strength at high temperatures.
c. The adhesive should have good coating and thickness consistency.
d. The adhesive should be used during its prescribed shelf life.
e. The adhesive should harden rapidly
f. The adhesive must not be contaminated.
g. The adhesive should have excellent insulation characteristics.
h. The adhesive should not be toxic and have no emission of toxic gasses.
（2）The recommended amount of adhesives is as follows;
Figure
212/316 case sizes as examples
0.3mm min
a
b
c
100 ～120 μm
Adhesives should not contact the pad
99
PRECAUTIONS
4/6
Precautions on the use of Multilayer Ceramic Capacitors
Stages
4. Soldering
Precautions
Technical considerations
Selection of Flux
1-1. When too much halogenated substance（Chlorine, etc.）content is used to activate
the flux, or highly acidic flux is used, an excessive amount of residue after soldering
may lead to corrosion of the terminal electrodes or degradation of insulation resis-
tance on the surface of the capacitors.
1. Since flux may have a significant effect on the performance
of capacitors, it is necessary to verify the following condi-
tions prior to use;
（1）Flux used should be with less than or equal to 0.1 wt%
（equivelent to chroline）of halogenated content. Flux
having a strong acidity content should not be applied.
（2）When soldering capacitors on the board, the amount of
flux applied should be controlled at the optimum level.
（3）When using water-soluble flux, special care should be
taken to properly clean the boards.
1-2. Flux is used to increase solderability in flow soldering, but if too much is applied, a
large amount of flux gas may be emitted and may detrimentally affect solderability. To
minimize the amount of flux applied, it is recommended to use a flux-bubbling system.
1-3. Since the residue of water-soluble flux is easily dissolved by water content in the
air, the residue on the surface of capacitors in high humidity conditions may cause a
degradation of insulation resistance and therefore affect the reliability of the compo-
nents. The cleaning methods and the capability of the machines used should also be
considered carefully when selecting water-soluble flux.
4
Soldering
1-1. Preheating when soldering
Temperature, time, amount of solder, etc. are specified in ac-
cordance with the following recommended conditions.
Heating: Ceramic chip components should be preheated to within 100 to 130℃ of the
soldering.
Cooling: The temperature difference between the components and cleaning process
should not be greater than 100℃.
Ceramic chip capacitors are susceptible to thermal shock when exposed to rapid or concen-
trated heating or rapid cooling. Therefore, the soldering process must be conducted with
great care so as to prevent malfunction of the components due to excessive thermal shock.
Recommended conditions for soldering
[Reflow soldering]
Sn-Zn solder paste can affect MLCC reliability performance.
Please contact us prior to usage.
Temperature profile
Temperature（℃）
（Pb free soldering）
300
Peak 260℃ max
10 sec max
200
100
0
Gradually
cooling
Preheating
150℃
60 sec min
Heating above 230℃
40 sec max
※Ceramic chip components should be preheated to
within 100 to 130℃ of the soldering.
※Assured to be reflow soldering for 2 times.
Caution
1. The ideal condition is to have solder mass （fillet）controlled to 1/2 to 1/3 of the
thickness of the capacitor, as shown below:
Capacitor
Solder
PC board
2. Because excessive dwell times can detrimentally affect solderability, soldering du-
ration should be kept as close to recommended times as possible.
[Wave soldering]
Temperature profile
Temperature（℃）
（Pb free soldering）
300
Peak 260℃ max
10 sec max
200
100
0
Gradually
cooling
Preheating
150℃
120 sec min
※Ceramic chip components should be preheated to
within 100 to 130℃ of the soldering.
※Assured to be wave soldering for 1 time.
※Except for reflow soldering type.
Caution
1. Make sure the capacitors are preheated sufficiently.
2. The temperature difference between the capacitor and melted solder should not be
greater than 100 to 130℃
3. Cooling after soldering should be as gradual as possible.
4. Wave soldering must not be applied to the capacitors designated as for reflow sol-
dering only.
101
PRECAUTIONS
5/6
Precautions on the use of Multilayer Ceramic Capacitors
Stages
Precautions
Technical considerations
[Hand soldering]
4. Soldering
ꢀTemperature profile
Temperature（℃）
（Pb free soldering）
400
300
200
350℃ max
3 sec max
Gradually
cooling
⊿Ｔ
4
100
0
60 sec min
（※⊿Ｔ≦190℃（3216Type max）, ⊿Ｔ≦130℃（3225
Type min）
）
直
※It is recommended to use 20W soldering iron and
the tip is 1φor less.
※The soldering iron should not directly touch the
components.
※Assured to be soldering iron for 1 time.
Note: The above profiles are the maximum allowable
soldering condition, therefore these profiles are
not always recommended.
Caution
1. Use a 20W soldering iron with a maximum tip diameter of 1.0 mm.
2. The soldering iron should not directly touch the capacitor.
5.Cleaning
Cleaning conditions
1. The use of inappropriate solutions can cause foreign substances such as flux residue
to adhere to the capacitor or deteriorate the capacitor's outer coating, resulting in a
degradation of the capacitor's electrical properties（especially insulation resistance）.
2. Inappropriate cleaning conditions（insufficient or excessive cleaning）may detrimen-
tally affect the performance of the capacitors.
1. When cleaning the PC board after the capacitors are all
mounted, select the appropriate cleaning solution according
to the type of flux used and purpose of the cleaning（e.g.
to remove soldering flux or other materials from the produc-
tion process.）
2. Cleaning conditions should be determined after verifying, （1）Excessive cleaning
through a test run, that the cleaning process does not affect
the capacitor's characteristics.
In the case of ultrasonic cleaning, too much power output can cause excessive vibra-
tion of the PC board which may lead to the cracking of the capacitor or the soldered
portion, or decrease the terminal electrodes' strength. Thus the following conditions
should be carefully checked;
Ultrasonic output
Below 20 W/ℓ
Below 40 kHz
Ultrasonic frequency
Ultrasonic washing period 5 min. or less
6.Post cleaning processes
1. With some type of resins a decomposition gas or chemical
reaction vapor may remain inside the resin during the hard-
ening period or while left under normal storage conditions
resulting in the deterioration of the capacitor's performance.
2. When a resin's hardening temperature is higher than the
capacitor's operating temperature, the stresses generated by
the excess heat may lead to capacitor damage or destruction.
The use of such resins, molding materials etc. is not recom-
mended.
Breakaway PC boards（splitting along perforations）
1. When splitting the PC board after mounting capacitors and
other components, care is required so as not to give any
stresses of deflection or twisting to the board.
7.Handling
2. Board separation should not be done manually, but by us-
ing the appropriate devices.
Mechanical considerations
1. Be careful not to subject the capacitors to excessive me-
chanical shocks.
（1）If ceramic capacitors are dropped onto the floor or a
hard surface, they should not be used.
（2）When handling the mounted boards, be careful that the
mounted components do not come in contact with or
bump against other boards or components.
103
PRECAUTIONS
6/6
Precautions on the use of Multilayer Ceramic Capacitors
Stages
Precautions
Technical considerations
8.Storage conditions
Storage
1. If the parts are stored in a high temperature and humidity environment, problems
such as reduced solderability caused by oxidation of terminal electrodes and dete-
rioration of taping/packaging materials may take place. For this reason, components
should be used within 6 months from the time of delivery. If exceeding the above
period, please check solderability before using the capacitors.
1. To maintain the solderability of terminal electrodes and to
keep the packaging material in good condition, care must
be taken to control temperature and humidity in the storage
area. Humidity should especially be kept as low as possible.
・Recommended conditions
4
Ambient temperature
Humidity
Below 30℃
Below 70% RH
The ambient temperature must be kept below 40℃. Even
under ideal storage conditions capacitor electrode solder-
ability decreases as time passes, so should be used within
6 months from the time of delivery.
・Ceramic chip capacitors should be kept where no chlorine or
sulfur exists in the air.
2. The capacitance value of high dielectric constant capacitors
（type 2 &3）will gradually decrease with the passage of time,
so this should be taken into consideration in the circuit design.
If such a capacitance reduction occurs, a heat treatment of
150℃ for 1hour will return the capacitance to its initial level.
105
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